Cache on MCU
In this post, we will cover the CACHE on the ARM Cortex-M7 series.
Modern embedded systems performance and efficiency are critical factors. Of course, one of these key components that significantly enhances the performance of MCU is the CACHE. Caching is a technique used to reduce the time CPU spends accessing data from main memory.
Overview
In ARM Cortex-M7, the Instruction Cache (I-CACHE) and Data Cache (D-CACHE) work independently to store instructions and data, respectively. In most case, icache enables device to achive close to zero wait state performance. While the dcache enables device to achieve optimum performance on external memory data accesses.
You can see the M7 has seperate buses for instructions and data, which allows CPU to access instructions and data simutaneously, enhancing overall performance and efficiency.
| Cache | Size | Function | Policies |
|---|---|---|---|
I-Cache | The I-Cache typically ranges in size from 16 KB to 64 KB and is 4-way set-associative. | The I-Cache stores instructions fetched from the main memory, allowing the CPU to execute instructions more quickly. By keeping frequently used instructionsin the cache, the system reduces the need for repeated memory accesses. | |
D-Cache | Similar to the I-Cache, the D-Cache also ranges from 16 KB to 64 KB and is 4-way set-associative. | The D-Cache stores data read from or written to the main memory, decreasing data access latency. This is crucial for operations that require frequent data reads and writes. | The D-Cache commonly uses a write-back policy, meaning data is first written to the cache and later written back to the main memory, improving write efficiency. |
Cache Controller
Control Registers: The cache controller manages both the I-Cache and D-Cache through a set of control and status registers. These registers can enable or disable the caches, configure cache operations, and provide status information. Maintenance Operations: The cache controller supports various maintenance operations, including: Invalidate: Removing entries from the cache. Clean: Writing back dirty cache lines to the main memory. Clean and Invalidate: Combining both operations to ensure data consistency.
Memory Protection Unit (MPU) Integration
MPU Regions: The MPU can define memory regions with specific cache policies, such as cacheable or non-cacheable regions.
Cache Coherence and Consistency
Coherence: Ensures that data in the cache is consistent with the main memory, particularly important in systems with DMA or peripherals that access memory directly.
Performance Considerations
Latency Reduction: The primary goal of the caches is to reduce latency for both instruction fetches and data accesses. Throughput Improvement: By keeping frequently accessed data and instructions in the cache, the overall system throughput is improved. Impact of Cache Misses: A cache miss, when the CPU requests data not present in the cache, results in fetching the data from the main memory, which introduces latency and affects performance.
What is Cache Hit and Cache Miss
Cache hit and cache miss are terms used to describe cache efficiency in ARM Cortex M7 cache system.
Cache Read
In case of reading the cache, we have two terms as following:
- Cache Hit
A cache hit occurs when the processor attempts to read data from the cache, and the data is found in the cache. This means the data is already stored in the cache from a previous read or write operation, allowing the processor to access the data much faster than if it had to retrieve it from the main memory.
- Cache Miss
A cache miss occurs when the processor attempts to read data from the cache, but the data is not found in the cache. This means the data is not currently stored in the cache, and the processor must retrieve the data from the slower main memory. This results in a delay as the data is fetched from the main memory and possibly stored in the cache for future access.
Cache Writing
In case of writing, the cache hit can be applied when the data to be written is found the cache, depending on the write policy, it will behave differently.
What is Dirty Bit
The dirty bit indicates if the cache has been modified (dirty) or not modified (clean). Each cache line (block) in the data cache has an associated dirty bit.
This dirty bit is used in writing to the memory since the writing won’t happen unless the dirty bit is set (dirty), this will reduce the writing operation to the main memory.
Cache Policies
The cache policies has the following four policies:
- Write through.
- Write back.
- Write allocate.
- Read allocate.
Write Through Cache Policy
Definition
The write-through policy ensures that every write operation updates both the cache and the main memory simultaneously. This means that whenever the processor writes data to the cache, it also writes the same data to the main memory.
Characteristics
- Data Consistency: Since every write operation updates both the cache and main memory, the data in the cache and main memory is always consistent. There is no need to worry about synchronizing the cache with the main memory later.
- Simplicity: The write-through policy is simpler to implement compared to the write-back policy because it eliminates the need for dirty bits and the complex logic required to manage them.
- Lower Latency for Reads: Since data in the cache is always up-to-date with the main memory, read operations can always fetch the most recent data from the cache, which is faster than accessing the main memory.
- Higher Memory Bandwidth Usage: The downside of the write-through policy is that it can lead to higher memory bandwidth usage. Every write operation generates traffic to the main memory, which can be a bottleneck, especially in systems with high write frequencies.
Write-Through in ARM Cortex-M7
In the ARM Cortex-M7 processor, the write-through cache policy can be configured for the data cache. Here’s how it typically works:
- Write Operation (Cache Hit): When the processor writes data and the data is already in the cache (cache hit), the data is written to both the cache and the main memory. This ensures that the cache and the main memory are always synchronized.
- Write Operation (Cache Miss): When the processor writes data and the data is not in the cache (cache miss), depending on the write allocation policy, the data may be written directly to the main memory or the data block may be fetched into the cache first and then written. In a write-through policy, this is usually direct to memory.
- No Dirty Bits: Since every write operation updates both the cache and the main memory, there are no “dirty” cache lines. Every cache line is clean because it always matches the corresponding main memory location.
Write Back Cache Policy
Definition
The write-back policy defers writing modified data in the cache to the main memory until it is absolutely necessary, typically when the cache line is evicted to make room for new data. This means that the write operation updates only the cache initially, and the main memory is updated later.
Characteristics
- Data Consistency: The cache and main memory are not always consistent. The data in the cache can be different from the data in the main memory if the cache has been modified (written to) and not yet written back to the main memory.
- Efficiency: Write-back caching can improve system performance because write operations complete quickly by updating only the cache. The main memory write is deferred and may occur less frequently, which reduces memory traffic and saves time.
- Use of Dirty Bits: Write-back caches use dirty bits to keep track of which cache lines have been modified. A dirty bit is set when a cache line is written to, indicating that this line needs to be written back to the main memory before it can be evicted.
- Cache Line Eviction: When a cache line is evicted (to make space for new data), if the dirty bit is set, the data in the cache line is written back to the main memory to ensure consistency.
Write-Back in ARM Cortex-M7
In the ARM Cortex-M7 processor, the write-back cache policy is implemented for the data cache. Here’s how it typically works:
- Write Operation (Cache Hit):
- When the processor writes data and the data is already in the cache (cache hit), the data is written only to the cache.
- The dirty bit for that cache line is set to indicate that the data has been modified and is different from the main memory.
- Write Operation (Cache Miss):
- If a write operation causes a cache miss (the data to be written is not in the cache), the relevant block of data is brought into the cache (causing a read miss), and then the write operation updates the cache. The dirty bit is set for the updated cache line.
- Cache Line Eviction:
- When a cache line with its dirty bit set (indicating modified data) needs to be evicted to make room for new data, the modified data is written back to the main memory. The dirty bit is then cleared, and the cache line can be replaced with new data.
- Cache Maintenance:
- Cache maintenance operations, such as cleaning, invalidating, and cleaning and invalidating, are used to manage the cache and ensure data consistency. For example, cleaning the cache writes back all dirty cache lines to the main memory without invalidating them.