Cache on MCU (Cont)

(Cont)

Cache Policies

Write allocate Cache Policy

The write allocate policy dictates that when a write miss occurs (i.e., the data to be written is not currently in the cache), the cache line containing the target memory address is loaded into the cache, and then the write operation is performed on the cache.

How It Works

1. Write Miss:
   • Cache Miss Occurs: When the processor tries to write to a memory address that is not present in the cache, a cache miss occurs.
   • Load Data into Cache: The cache line that contains the target memory address is fetched from the main memory and loaded into the cache.
   • Write Data to Cache: The write operation is then performed on the newly loaded cache line.
2. Subsequent Writes: Once the cache line is in the cache, subsequent writes to addresses within that line will be cache hits, allowing for faster write operations.

Write Allocate

In the ARM Cortex-M7 processor, the write allocate policy can be configured for the data cache. Here’s how it typically works:

1. Handling Write Misses:
   • On a write miss, the ARM Cortex-M7 fetches the required cache line from the main memory and loads it into the cache.
   • The processor then performs the write operation on the loaded cache line.
   • Depending on whether the write-back or write-through policy is in use, subsequent writes will either set the dirty bit (write-back) or write to both the cache and main memory (write-through).
2. Integration with Write-Back:
   • Write-Back + Write Allocate: This combination is common. When a write miss occurs, the line is brought into the cache, written to, and marked as dirty. The write-back policy will later handle writing this modified data back to the main memory.
3. Integration with Write-Through:
   • Write-Through + Write Allocate: When a write miss occurs, the line is brought into the cache, written to, and the data is simultaneously written to the main memory. This ensures that the cache and main memory are always in sync.

Example: Write Allocate Policy

Assume the processor wants to write the value 20 to memory address 0x20001000, but the corresponding cache line is not currently in the cache (write miss).

Initial state

| Location  | Value          |
|-----------|----------------|
|Cache      |   Not Present  |
|Main Memory|   10           |

Write operation

CPU writes 20 -> Write Miss -> Fetch cache line from Main Memory -> Load cache line into Cache -> Write 20 to Cache


Final state (Write-Back + Write Allocate)

| Location  | Value          |
|-----------|----------------|
|Cache      | 20 (Dirty = 1) |
|Main Memory|   10           |

The cache line is first loaded into the cache, then updated. Since write-back is used, the main memory is updated later when the cache line is evicted or cleaned.

Final state (Write-Through + Write Allocate)


| Location  | Value          |
|-----------|----------------|
|Cache      | 20             |
|Main Memory|   10           |


After loading the cache line, the write updates both the cache and the main memory.

Key Point: Write Allocate determines what happens on a write miss. The subsequent write behavior (cache only or cache + memory) is determined by the write policy (Write-Back or Write-Through).

Read Allocate Cache Policy

The read allocate policy dictates that when a read miss occurs (i.e., the data to be read is not currently in the cache), the cache line containing the target memory address is fetched from the main memory and loaded into the cache. The read operation is then completed using the data in the cache.

How It Works

1. Read Miss:
   • Cache Miss Occurs: When the processor tries to read a memory address that is not present in the cache, a cache miss occurs.
   • Load Data into Cache: The entire cache line that contains the target memory address is fetched from the main memory and loaded into the cache.
   • Complete Read Operation: The processor completes the read operation using the data now present in the cache.
2. Subsequent Reads: Once the cache line is loaded into the cache, subsequent reads to addresses within that line will result in cache hits, providing faster access to the data.

Read Allocate

In the ARM Cortex-M7 processor, the read allocate policy is typically used for both the instruction cache and the data cache. Here’s how it typically works:

1. Handling Read Misses:
   • On a read miss, the ARM Cortex-M7 fetches the required cache line from the main memory and loads it into the cache.
   • The read operation is then completed using the loaded cache line.
   • Subsequent reads to the same or nearby addresses within that cache line will be cache hits, improving read access times.
2. Integration with Cache Policies:
   • Read-Allocate + Write-Back: When a read miss occurs, the line is brought into the cache. Subsequent writes to this line will mark it as dirty, and the write-back policy will later handle writing this modified data back to the main memory.
   • Read-Allocate + Write-Through: When a read miss occurs, the line is brought into the cache. Subsequent writes will update both the cache and the main memory, ensuring consistency between the two.

Example: Read Allocate Policy

Assume the processor wants to read memory address 0x20001000, but the corresponding cache line is not currently in the cache (read miss).

Initial state

| Location  | Value          |
|-----------|----------------|
|Cache      | Not Present    |
|Main Memory|   10           |

Read operation

CPU reads 20 -> Read Miss -> Fetch cache line from Main Memory -> Load cache line into Cache -> Return requested data to CPU

Final state

| Location  | Value          |
|-----------|----------------|
|Cache      |  10            |
|Main Memory|   10           |

The requested cache line is now stored in the cache. Any subsequent read to the same address (or another address within the same cache line) becomes a cache hit, avoiding another memory access.

For example:

1st read:
CPU -> Memory -> Cache ->CPU   (Cache Miss)

2nd read:
CPU -> Cache -> CPU              (Cache Hit)

Key Point: Read Allocate determines what happens on a read miss. The missed cache line is fetched from main memory and stored in the cache so that future accesses to the same cache line can be served more quickly.

Cache Coherency