Introduction to Memory Protection Unit
MPU is an optional component for the memory protection. The MPU must be programmed and enabled before using it. If the MPU is not enabled, there is no change in the memory system behavior. And this series describe how to manage MPU in these STM32 products. Now, let’s dive into the very first section.
Overview
The MPU can be used to make the system more robust and secure by:
- prohibiting the user applications from corrupting data used by critical tasks (such as the operating system kernel)
- defining the SRAM memory region as a non-executable (execute never XN) to prevent code injection attacks
- changing the memory access attributes
The MPU can be used to protect up to 16 memory regions. In Armv6 and Armv7 architect (Cortex-M0+, M3, M4 and M7), these regions in turn can have eights subregions, if the region is at least 256 bytes. The exact amount of regions protected can vary between core and devices. The sub-regions are always of equal size, and can be enabled or disabled by a sub-regions number. Because the minimum region size is driven by the cache line length (32 bytes), eight subregions of 32 bytes correspond to a 256-byte size. The regions are numbered 0 to 15. In addition, there is a region called the default region with an id of -1. All the 0-15 memory regions take priority over the default region. The regions can overlap, and can be nested. The region 15 has the highest priority and the region 0 has the lowest one and this governs how overlapping the regions behave. The priorities are fixed, and cannot be changed. In Armv8 architecture (Cortex-M33 and M55) the regions are defined using a base and a limit address offering flexibility and simplicity to the developer on the way to organize them. Additionally, Cortex-M33 and M55 do not include subregions as the region size is now more flexible. The figure below shows an example with six regions. This example shows the region 4 overlapping the regions 0 and 1. The region 5 is enclosed completely within the region 3. Since the priority is in an ascending order, the overlap regions (in orange) have the priority. So, if the region 0 is writeable and the region 4 is not, an address falling in the overlap between 0 and 4 is not writeable.
